--test1.e

<'

import ../examples/vv_ahblite_config;
import ../e/vv_ahblite_master_seq_lib;

extend M0 MAIN vv_ahblite_master_sequence {
    
    !wrseq : SINGLE_WRITE vv_ahblite_master_sequence;
    !rdseq : SINGLE_READ vv_ahblite_master_sequence;

        
    num : uint;
       keep num in [50..100];
           
    body() @driver.clock is only {
   -- 	for i from 1 to num do {
    		
    		do wrseq;
    		
    		
    		
    		do rdseq;
//            do wrap4 keeping{
//            	.busy == i-1;
//            	.start_address == 0x34;
//            	.write == i%2;
//            };
//            

         
  --  	};
    }; 

}; 


'>